The nearer the system operates to the limits of device and interconnection technology, the greater the chances of serious timing errors.

To utilize the fast potential operating speed of modern digital devices, the functional design, the interconnection and the power distribution system cannot be separated. Fast pulse edges cause crosstalk, transmission line effects, power supply transients, and ground bounces even when the best interconnection design practices are followed.

Figure 1:

Noise sources and noise transmission mechanisms. Noise source effects tend to increase as system speed increases.

Advanced DSOs, such as LeCroy’s LC500 family, present a variety of ways to analyze digital systems. Fast sampling DSOs are becoming an indispensable complement to logic analyzers for serious troubleshooting. This article will illustrate some applications of DSOs in high speed digital troubleshooting.

Probe loading effect

To correctly measure high frequency signals such as those from digital circuits, probes with high impedance and low capacitance should be used. Each probe presents some inherent capacitance (cable capacitance) and inductance (ground lead). The RC constant of the probe will alter signal shape (acting as low pass filter) and thus impact on measurement accuracy.

Secondary effects such as resonance effects should not be dismissed. For example, a probe with a ground lead inductance of 1 m H and a combined capacitive loading of 10 pF will yield a resonant frequency around 22 MHz. Because of these effects, DSO manufacturers provide also active FET probes. FET probes are optimized to offer high impedance at high frequencies to minimize loading effects.

Fig. 2 shows the effect of using a passive vs. an active probe. The edges on trace B obtained with a 1 GHz probe clearly reveal distortion effects that are hidden with the passive probe (trace A). Similarly, the ringing effect on the falling edge is attenuated by the passive probe.

Main noise sources in digital systems

Because of the interconnection of system parts, induced noise will propagate across the circuit via a series of mechanisms. System noise sources typically are connectors, PC board trace layout, IC package geometry, power and ground plane. Noise source mechanisms consist of reflections, crosstalk, ground shifts, inductive glitches. Some of the noise sources are illustrated in Fig. 1.

Figure 2:

Reflections seen at various distances on a data bus line. Traces A and B show the same signal. Trace A was captured with a 300 MHz passive probe, Trace B with a 1GHz active probe. Edge distortions are clearly recognizable.

Transmission line effects

Signals are well-behaved when the signal source impedance, signal line impedance, and load impedance are very closely matched and the line has only one source and one load with no discontinuities, branches or stubs. In such cases, a signal very much like the signal launched at the source can be observed at the load. If the signal source, line, and load are not matched then or if the circuit topology does not consist of the ideal case of a source and a load, then the signal quality will degrade due to transmission line ringing and reflection effects.


Additional time beyond the one-way propagation delay of the lines will be required for signals to settle. As un-terminated lines increase in length beyond the critical line length, the signal quality progressively degrades and takes longer to stabilize. Often it is impractical to terminate all signals in most digital systems since terminations require additional components and may dissipate additional power. Thus in most systems, additional time beyond the one-way line propagation time must be allowed for signals to settle (rule of thumb five time line delays for un-terminated lines to settle). Fig. 2 shows some typical signals at various points o a transmission line. Excessive spurious ringing, as seen on trace C, can potentially impair system reliability.


Crosstalk is the voltage developed on signal lines when nearby lines change state. Crosstalk occurs due to capacitive and inductive coupling between adjacent or nearby lines. It is a function of the separation between signal lines, the linear distance that signals lines run parallel with each other, and the height above a ground, or other reference, plane.

The faster edge rates of present day logic devices greatly increase the possibility of coupling or crosstalk of digital devices. Increased coupling, plus faster device response, greatly increases the possibility that system operation will be degraded by crosstalk.

Common noise problems

Ground bouncing

Fast edges of current logic devices cause large, high-frequency transient load currents. Large load currents mean large currents in the ground and power connection of the switching devices. These large currents in conjunction with the inductance of the package leads, bond wires, and chip metallization cause large shifts in chip reference and power supply levels. These level shifts are called ground bounces. If the level shifts are large enough, they may cause:

  • Logic errors in the switched device or at the inputs of devices connected to signals that originate from the switched device
  • Nonmonotic transitions on outputs which can cause double clocking if the outputs are used as clock signals
  • Degradation of propagation delays due to supply voltages across the switched device being reduced which reduces drive

Fig. 3 shows a ground bounce effect at the trailing edge of trace 3. Ground bouncing can be minimized by careful synchronous design, lower pin inductance, etc..

Figure 3:

Propagation delay histogram. Statistical methods provide a means for quantifying delay variations in a real time environment. The variation ranges between - 26.2 and 12.8 ns.

Induced switching noise

Induced switching noise refers to the noise induced on the supply rails by the switching action of each logic gate in the circuit. As each gate changes state, a current pulse is taken from the supply pins because of the different device currents required in each state, the external loading, the transient caused by charging or discharging the node capacitance, and the conduction overlap in the totem-pole output stage. All these effects are present in all logic families to some extent, although CMOS types suffer little from the first two. In most cases, the node capacitance charging current dominates, more so with higher-speed circuits. The capacitance Cn must be charged with a current of Cn*deltaV/deltat.

For example, a 74ALS-series gate with a deltav/deltat of 1V/ns will require a 50 mA current pulse when charging a 50pF node capacitance. The significance of the supply current spike is that it causes a disturbance in the supply voltage and also in the ground line, because of the inductive reactance of the lines. A pulse with a di/dt of 50mA/ns through a track inductance of 20 nH will (2.5 cm track) will generate a voltage pulse of 1 V peak, which is approaching the noise margin of fast logic. While voltages spikes can be attenuated by proper decoupling, ground line disturbances are more threatening. Pulses on a high-impedance ground line can easily exceed the noise threshold and cause spurious switching of innocent gates. Only, if a low-inductance ground system is maintained, can this problem be minimized.

Figure 4:

Switching noise on Power supply and ground rails due to synchronous switching. The amount of noise on the ground noise could upset system integrity by leading to erroneous triggering

Timing problems

Timing violations

For system performance goals to be met, realistic worst-case propagation delays of each component in each signal path, plus the physical propagation delays and settling time of each interconnection within the paths, must be determined and factored into the projected operation speed. Signal interconnection and settling time delays are a significant part of most signal propagation delay paths when system operating speeds approach 20 MHz or greater.

Traditionally, worst case analysis is used to analyze digital circuits and interconnection delays. When a worst-case analysis shows that all paths meet their timing requirements widths some margin, the system should perform in a reliable manner. Since not all delay effects are usually accounted for, some margin (20.. 50%) is required. The disadvantage of worst case timing analysis is that it produces conservative results which may cause circuits to be overdesigned or system performance goals to be reduced.

Statistical timing analysis is an alternate approach to worst-case analysis. Statistical analysis provides a means for quantifying the risks of performance and manufacturing goals vs. timing parameter variations. Statistical methods are often the only realistic approach for timing paths with many components and multiple path. Fig. 3 shows the histogram of a propagation delay histogram. The delay range provides the designer an overview of the extent of the variation.

Figure 5:

Advanced DSOs offer a wide range of triggering possibilities to quickly capture various anomalies. Here the DSO is set to trigger on a pattern by constraining the interval width pattern 1H*2L.


At asynchronous interfaces there is always the problem of synchronizing devices going into metastable states. When metastable malfunctions occur in digital devices, outputs may linger for some indeterminate period in the unknown-logic-level region, or they may go to a valid logic level but be unstable and not remain in that state. The possibility of metastable conditions of clocked devices is inherent and difficult to prevent at asynchronous interfaces. The recovery time for a part that goes into a metastable state can be much longer than the specified propagation delay for the part in the normal operating mode. The higher the system speed, the greater the concern since the higher the speed, the less time there is for recovery. The probability of occurrence of metastable operation depends on the device technology, clock frequency, and frequency and phase of the input data.

Fig. 6 shows metastable conditions. The signal was acquired in color graded persistence mode. White colors indicate areas where the signal recurs more often.

FiguRe 6:

Metastable states induced at an asynchronous interface. Color graded persistence reveals signal Metastability distribution trends.


As clock frequencies increase, signal integrity problems and timing problems will increase. Advanced DSOs with high bandwidth and sample rates provide designers with new possibilities to ease digital circuit troubleshooting. The LeCroy LC500 series, in particular, offers designers a wide range of triggering and statistical tools to quickly and conveniently analyze and verify integrity of digital signals.