The PCI Express® protocol was designed to be layout-agnostic with respect to lane ordering and lane polarity. However, when using a protocol analyser to monitor a PCI Express bus, the end user may need to be more aware of the impact of the design layout in respect to polarity and lane ordering.

This document reviews some of the factors which may affect protocol analysis, and how to configure the analyser for such conditions. For clarity, the examples are illustrated using x4 links, however the principle is the same for x2, x4, x8, x16 links and for x1 links with the exception of lane reversal at x1.


PCI Express uses a differential signalling technology and the two signal wires are designated positive and negative (D+ and D-). Normally it would be expected to connect the transmitters D+ directly to the receivers D+ (and D- to D-) as shown in Figure 1. For clarity the examples shown are illustrated on a x4 link, however this is scalable to all valid link widths.

A system which has no polarity or lane reversal throughout the link would look similar to Figure 1.

NoteThe “Connector” illustrated below and in the following diagrams is typically the PCIe connector on the motherboard (or VPX/AMC/XMC/MiniCard chassis) where the interposer in inserted to collect the data traffic. In some situations this could also be an external cable between host and device.

Figure 1:

A simple 4-lane link

Figure 2 shows a system in which two of the lanes have polarity inversion with respect to the receiver. In this case the endpoint will detect a polarity inversion on Lane#0 and Lane#2 and adjust its inputs accordingly during the training phase of link bring up. By contrast an observer at the connector would only see lane#0 as inverted because the layout that caused the inversion in Lane#2 happened after the connector.

Figure 2:

Some lanes with reverse polarity

For the general operation of the link these layout effects have no discernible effect, because the PCI Express specification anticipates and allows for this, providing a mechanism in the link training sequence to adjust the receiver. This does provide some complexity if observations are made at the connector after the link training has already been established. Simply being aware of the polarity detected by the receiver may not be sufficient (but usually is) to configure the receivers of a passive observer after link training has been completed.

A protocol analyser observing mid-link could be set to auto configure lane polarity, and if the link training sequence is observed the automatic configuration will be successful. The learned configuration could then be applied to the recording options for future observations. This has two advantages: (1) the analyzer will be able to record a link correctly if recording is commenced some considerable time after the link has been established; and (2) selecting a fixed configuration will improve the lock time of the analyser if the link is interrupted for some reason (for example, a change of power state).

The resulting (fixed) setup for the analyser in this example would be to set Lane reversal = off and Polarity inversion on lane 0 only. Polarity inversion is not needed on the analyser for Lane#2 because it occurs after the observation point.

Figure 3:

Transmitter Lane Reversal

Sometimes the pin-out of a device and the placement on the board makes it difficult to route the signals cleanly to the connector without crossing the wires. In this case, PCI Express allows for a complete reversal of the physical lane ordering between the device and the connector/target device. The rules require that the lanes are still sequentially ordered but can be logically reversed. In the layout depicted in Figure 3, the transmitter pins have been connected such that the pin designated Lane#3 has been connected to Lane#0 of the connector. The remaining pairs are connected in order until Transmitter Lane#0 is connected to the connector Lane#3. Physically the receiver is unaware of this re-ordering, because its Lane#0 is connected to the connector pin designated as Lane#0 by the specification.

However during link training the host and device will negotiate a logical link ordering that can be used to ensure the STP or SDP symbols can be correctly detected.

Figure 4:

Normal and reversed lane ordering

When the lane reversal is set incorrectly on an analyser the user will only be able to record ordered sets. Ordered sets such as Training or Skip sequences transmit the same symbol simlutaneously on all active lanes, and consequently they are not effected by lane ordering. However DLLP and TLP packets are sensitive to lane ordering and must start with an SDP or STP symbol in Logical lane#0. If these symbols are being transmitted on physical lane#3 with respect to the analyser input and lane reversal has not been configured, an analyser will detect no valid packet start.

If a simple trace capturing the configuration phase of the training sequence is made (e.g., trigger on TS2), it can be readily determined if lane reversal is required. If lane reversal is detected in one or both directions for the current configuration, it is simply a matter of checking the appropriate lane reversal box. Alternatively if you are using a model of analyser that supports Lane Swizzling (e.g., Summit T3-16), you could use the automatic swizzle to perform the lane reversal (please refer to user manual for details).

Taking this a step further, Figure 5 shows a system with mixed polarity and lane reversal. While this may not be common, since most systems are simple oneto-one connections, it is possible to encounter such implementations. In this example the correct settings for the analyser at the connector would be Lane Reversal = True, and Lane#0 and Lane#2 inverted Polarity (note the setting for polarity in the recording options refer to physical not logical lanes).

Figure 5:

Mixed polarities and lane reversal

Taking this now to an extreme situation (Figure 6), where the end-to-end connectivity is electrically aligned, however the observable point (at the connector) is not wired in a standard way. First impressions may suggest the layout designer just had a bad day and that this design would cause interoperability problems with standard devices, if plugged into the connector. However, this situation arises most frequently when a Mid-bus probing footprint is used and circumstances have led to a complex layout for the exposed surface pads.

Figure 6:

Non-standard probing alignments

In this situation you would need an analyser that supports “Lane Swizzling” (the ability to logically rewire the probe header to match the custom layout).

Figure 7:

Lane Swizzling as implemented in Summit T3-16 protocol analysers